Silicon has been used for fabrication of various semiconductor devices, including field effect transistor (FET) devices. The processing limit for silicon is generally considered to be about 10 nm line width. With the continuing demands to decrease the size of semiconductor devices while increasing speed and integration density, the silicon semiconductor material is gradually approaching its processing limits.
Graphene is a single atomic layer (i.e., a monolayer) of graphite. Graphene has a two-dimensional structure and conducts electricity in a planar direction. The graphene lattice includes carbon atoms arranged in a hexagonal array with a carbon-carbon bond angle of 120 degrees, a carbon-carbon bond length (ro,g) of 1.42 Å, and a lattice constant of about 2.46 Å. Graphene has high charge mobility of approximately 15000 cm2/Vs, high current carrying capability exceeding 1×108 A/cm2, and excellent thermal conductivity. Therefore, graphene is being investigated as a next-generation material for replacing silicon in various semiconductor devices, including FET devices.
Graphene is a zero energy band gap material (i.e., there is no energy gap between the conduction and valence bands of graphene). In contrast, semiconductor materials have an energy band gap between the conduction and valence bands. Because of its zero energy band gap, graphene has a very large off current and consequently a very small on/off ratio of an operating current (hereinafter “on/off ratio”). Such a low on/off ratio limits the large integration and high-speed operation of the FET device. Furthermore, due to the very large off current of graphene, the FET devices using unmodified graphene (i.e., large-area graphene) cannot be switched off and are not suitable for logic applications.
Various attempts have been made to modify (i.e., open) the band gap structure of graphene. One approach has been to constrain unmodified graphene in one dimension by cutting it into narrow ribbons of less than a few tens of nanometers, known as graphene nanoribbons. The energy band gap of graphene nanoribbons is inversely proportional to the width of the nanoribbon. Therefore, to obtain graphene having an energy band gap useful for conventional FET devices, very narrow graphene nanoribbons with well-defined edges are required. Thus far, it has been a challenge to manufacture graphene in the size of several nanometers with uniform width, reduced edge roughness, and excellent quality. Accordingly, despite their excellent characteristics, the integration of graphene nanoribbons into semiconductor devices such as FET devices has been limited.
Graphene-silicon hydride structures have been investigated for fabrication of triode devices, wherein the on/off ratio of about 105 may be achieved by adjusting the gate voltage to control the graphene-silicon Schottky barrier. Although graphene has a zero energy band gap, the absence of Fermi-level pinning at the interface of graphene and silicon allows the barrier's height to be turned to 0.2 eVs.
U.S. Pat. No. 8,247,806, issued Aug. 21, 2012, discloses an FET device having a graphene channel layer. Although graphene has a zero energy band gap, the on/off ratio of the FET device is increased by applying voltage to the gate structure, thereby changing the energy level of the Fermi surface.
There exists a need for a method of modifying the energy band gap of graphene to allow the use of graphene in semiconductor devices as a replacement for silicon-based materials.
Further, there exists a need for an FET device that is compatible with standard complementary metal oxide semiconductor (CMOS) processing technologies and manufacturable with minimum number of processing acts.